1. Field of the Invention
The present invention relates to a semiconductor device having a high-density, high-performance capacitor elements of large capacitance and high withstand voltage and which have little parasitic resistance and parasitic capacitance. The present invention also relates to a method of manufacturing the semiconductor device having such capacitor elements.
2. Background Art
A conventional method of manufacturing a semiconductor integrated circuit device having a built-in capacitor element will now be described.
FIG. 8 is a cross-sectional view showing one example of an conventional capacitor element formed in a semiconductor integrated circuit device.
In the drawing, reference numeral 1 designates a silicon substrate; 2c, 2d, and 2e designate interlayer insulating films; 3 designates a contact hole; 6 designates a first wiring layer; 12 designates a capacitor formation section; 17 designates an upper electrode of a capacitor element; 18 designates an interlayer insulating film; 19 designates a lower electrode of the capacitor element; and 20 designates an insulating film (i.e., a dielectric film) of the capacitor element.
In the example, an impurity-diffused layer, which is formed in the surface of the silicon substrate 1 simultaneously with formation of other circuit elements, is used as the lower electrode 19 of the capacitor element. As the upper electrode 17 of the capacitor element, a conductive film is used which is formed simultaneously with formation of a wiring layer, and is formed from a metal layer primarily constituted of aluminum or impurity-containing polysilicon. As an insulating film 20 interposed between the upper and lower electrodes 17, 19, a silicon oxide film or a silicon nitride film, which has a higher dielectric constant than the silicon oxide film, is used.
In a case where a metal layer, which is of the same metal layer as that used for the wiring layer, is used for the upper electrode 17, there are additionally required photolithography and etching processes for forming a hole in a capacitance formation area 12, aside from forming the other contact hole 3, in an interlayer insulating film between the lower surface of the metal layer and the silicon substrate 1.
In a case where a silicon nitride film is used as the insulating film 20 interposed between the upper and lower electrodes 17, 19, there are additionally required a process of depositing a nitride film by means of CVD, and photolithography and etching processes for patterning the deposited nitride film.
In a case where the silicon oxide film is used as the insulating film 20 interposed between the electrodes 17 and 19, the previously-described additional processes are unnecessary, although an oxidation process is required. However, the silicon oxide film is lower in dielectric constant than the silicon nitride film, and the area of the capacitance formation area 12 must be increased in order to ensure the same capacitance.
Alternatively, so long as the distance between the electrodes, i.e., the thickness of the insulating film 20 (a silicon oxide film), is reduced, the capacitance per unit area can be increased. However, this may results in a decrease in the withstand voltage of the capacitor element, which in turn causes an increase in leakage current.
Since an impurity-diffused layer is used for the lower electrode 19, parasitic capacitance between the silicon substrate 1 is added. Moreover, in case the impurity diffused layer works as an impurity-diffused layer for anther circuit element, the resistance can not be reduced. This results in addition of parasitic resistance to the capacitor element. To form an impurity-diffused layer designed specifically for use as a lower electrode of a capacitor element for the purpose of decreasing the resistance of the capacitor element, there are additionally required photolithography, etching, and impurity diffusion processes.
Even in a case where a conductive film, such as an impurity-containing polysilicon film, is used for the upper electrode 17, parasitic resistance poses a problem, as in the previous case. Unless the conductive film can work as a polysilicon film to be used for another circuit element, e.g., a gate electrode of MOS, there are additionally required a process of depositing a polysilicon film by means of CVD and photolithography, and etching processes for patterning the deposited polysilicon film, thus complicating the processes.
FIG. 9 is a cross-sectional view showing another example of an conventional capacitor element.
In the drawing, reference numeral 1 designates a silicon substrate; 6a and 6b designate wiring layers; 11 designates a hole for use in establishing connection with a lower electrode of the capacitor element; 12 designates a capacitance formation section; 18 designates a surface protective film; 21a designates a lower electrode of the capacitor element; 21b designates an upper electrode of the capacitor element; and 22a, 22b, 22c, and 22aa designate insulating films (i.e., silicon oxide films).
In this example, a capacitor element is formed on the interlayer insulating film 22a of the silicon substrate 1, on which other circuit elements are formed. Two-layer of impurity-containing polysilicon film are used as the upper and lower electrodes 21a, 21b of the capacitor element, and a silicon oxide film is used as the insulating film 22aa interposed between the electrodes 21a and 21b.
In this case, the parasitic capacitance between the lower electrode 21a and the silicon substrate 1 can be reduced. Since the impurity-containing polysilicon film is used for both the upper and lower electrodes 21a, 21b, parasitic resistance is added to the capacitor element, and manufacturing processes are complicated, as in the previously-cited case. Further, since the silicon oxide film is used as the insulating film 22aa interposed between the electrodes 21a and 21b, this conventional example also poses a problem, as in the previous case, in terms of capacitance, a withstand voltage, and a leakage current.